Radar scan converters typically translate the polar coordinates of data received by the radar set into the corresponding rectangular coordinates so that the data can be stored in an x-y memory. The x-y memory can then be scanned linearly to produce a video display.
In a standard video display of 525 lines by 512 pixels scanned at 30 frames per second, one pixel must be written each 100 ns. If the image is contained in a 512-line field of the display, and 64K memory chips are used for the x-y memory, four memory chips are required to store the entire 512.times.512 pixel image. The four memories are read out in parallel every 400 ns on the average, and the four pixels derived from the read-out are transferred to a buffer memory which is read onto the display screen by the video scan.
In the conventional memory configuration, the four 64K memory chips represent four adjacent pixels of the same video line. Consequently, four pixels can be read out of the x-y memory in parallel during each video read operation.
Each operational cycle of a radar scan converter must perform four functions: (1) read pixels stored in the x-y memory into the video buffer; (2) read corresponding pixels out of the radar buffer, and x-y memory, compare them, and write new pixel data into the x-y memory at the same location if appropriate; (3) generate the addresses for the read and write operations; and (4) if continuous fade (for tracking moving targets) is used, read, decrement, and rewrite selected pixels in the x-y memory.
In the standard hardware package for this type of application, the generation of a full random address coupled with a read or write operation requires about 200 ns. Subsequent read or write operations at the same location require only 100 ns.
It follows that in conventional scan converters, the reading of sixteen pixels out of the x-y memory in parallel groups of four consumes 800 ns. Inasmuch as the video monitor takes 1600 ns to scan sixteen pixels, 800 ns are available in conventional scan converters for the other functions described above.
A radar data read/modify/write operation consumes 300 ns, as the read and write operations take place at the same address. Likewise, a fade read/modify/write operation on four parallel pixels consumes 300 ns for the same reason. Thus, in the remaining 800 ns of a 1600 ns cycle, it is possible to do either two radar data writes and no fade, or one radar data write and one four-pixel fade.
In order to maintain the above-described functions within the time limits dictated by the video scan, it has thus previously been necessary either to perform the fade function in separate cycles, e.g. during the video retrace, or to reduce the rate at which radar data is written into the x-y memory, or to use more complex and expensive hardware.
Although the conventional system works well in conventional radars, modern high-resolution radars require even faster updating of radar data as well as smooth fades. With the conventional memory configuration, this entails even more hardware complexity and expense.